VILT for Xilinx FPGA


Our virtual instructor-led trainings (VILT) for Xilinx FPGA offer a unique and lively course experience. All courses are conducted live with a personal trainer using web conferencing software. This approach avoids time consuming and expensive business trips and aids in better course schedule integration into daily business. Practical labs on our remotely accessible real hardware enables omission of extra equipment on customer side. This unique feature helps in a better understanding of course contents and intensifies knowledge gain.

Current course offerings are listed in the following table. Please read our information on VILT courses and terms and conditions before registering to a course. You can register directly for a given course using the registration link provided in the table.

Please ask for a discount if you plan to book multiple courses.

Please do not hesitate to contact us in case you have any questions in relation to our courses.

Signal Integrity & Board Design

Class Title Location Duration Price Click to Register for
Board Design for UltraScale Series FPGAsVILT 2 sessions Request Info 2017/12/27-12/28
VILT 2 sessions Request Info 2018/03/26-03/27
Board Design for Xilinx 7 Series FPGAsVILT 2 sessions Request Info 2018/02/28-03/01
VILT 2 sessions Request Info 2018/05/28-05/29
Board Design for Xilinx ZYNQ-7000 SoCsVILT 2 sessions Request Info 2018/03/28-03/29
Signal Integrity for Xilinx FPGA Memory InterfacesVILT 2 sessions Request Info 2018/03/12-03/13
Signal Integrity for Xilinx FPGAs Serial Link InterfacesVILT 2 sessions Request Info 2018/03/19-03/20
Signal Integrity for Xilinx FPGAs
Part I – Essential Techniques
VILT 2 sessions Request Info 2018/01/24-01/25
VILT 2 sessions Request Info 2018/04/25-04/26
Signal Integrity for Xilinx FPGAs
Part II – Advanced Techniques
VILT 2 sessions Request Info 2018/01/31-02/01
VILT 2 sessions Request Info 2018/05/02-05/03

Networking

Class Title Location Duration Price Click to Register for
100G Ethernet InterfacesVILT Request Info Request Info
10G / 25G Ethernet InterfacesVILT Request Info Request Info
Ethernet StandardsVILT Request Info Request Info
Interlaken – Protocol and DesignVILT Request Info Request Info

Memory Interfaces

Class Title Location Duration Price Click to Register for
DDR2/DDR3 Interfacing in 7 Series FPGAs/SoCs
Part I – Memory Devices and Controller
VILT 2 sessions Request Info 2017/12/27-12/28
VILT 2 sessions Request Info 2018/04/04-04/05
DDR2/DDR3 Interfacing in 7 Series FPGAs/SoCs
Part II – Designing Memory Interfaces
VILT 2 sessions Request Info 2018/01/03-01/04
VILT 2 sessions Request Info 2018/04/11-04/12
DDR2/DDR3 Interfacing in 7 Series FPGAs/SoCs
Part III – Debugging Techniques and PCB Design
VILT 2 sessions Request Info 2018/01/10-01/11
VILT 2 sessions Request Info 2018/04/18-04/19
DDR3/DDR4 Interfacing in UltraScale Series FPGAs/MPSoCs
Part I – Memory Devices and Controller
VILT 2 sessions Request Info 2018/02/07-02/08
VILT 2 sessions Request Info 2018/05/09-05/10
DDR3/DDR4 Interfacing in UltraScale Series FPGAs/MPSoCs
Part II – Designing Memory Interfaces
VILT 2 sessions Request Info 2018/02/14-02/15
VILT 2 sessions Request Info 2018/05/16-05/17
DDR3/DDR4 Interfacing in UltraScale Series FPGAs/MPSoCs
Part III – Debugging Techniques and PCB Design
VILT 2 sessions Request Info 2018/02/21-02/22
VILT 2 sessions Request Info 2018/05/23-05/24

High-Speed Serial Interfaces

Class Title Location Duration Price Click to Register for
Debugging a PCI Express SystemVILT 2 sessions Request Info 2018/02/12-02/13
VILT 2 sessions Request Info 2018/05/14-05/15
Designing an Integrated PCI Express System
PCIe Gen2 in 7 Series FPGAs/SoCs
VILT 2 sessions Request Info 2018/01/29-01/30
VILT 2 sessions Request Info 2018/04/30-05/01
Designing an Integrated PCI Express System
PCIe Gen3 in UltraScale Series FPGAs/SoCs
VILT 2 sessions Request Info 2018/02/05-02/06
VILT 2 sessions Request Info 2018/05/07-05/08
PCI Express ProtocolVILT 2 sessions Request Info 2018/01/22-01/23
VILT 2 sessions Request Info 2018/04/23-04/24
PCI Express Virtualization with Xilinx DevicesVILT 2 sessions Request Info 2018/02/19-02/20
VILT 2 sessions Request Info 2018/05/21-05/22
Serial RapidIO
Part I – Protocol Specification
VILT 2 sessions Request Info 2018/02/26-02/27
VILT 2 sessions Request Info 2018/05/28-05/29
Serial RapidIO
Part II – Designing with sRapidIO IP Cores
VILT 2 sessions Request Info 2018/03/05-03/06
Serial Transceivers in 7 Series FPGAs/SoCs
Part I – Essential Techniques
VILT 2 sessions Request Info 2018/01/01-01/02
VILT 2 sessions Request Info 2018/04/02-04/03
Serial Transceivers in 7 Series FPGAs/SoCs
Part II – Transceiver Design Methodology
VILT 2 sessions Request Info 2018/01/08-01/09
VILT 2 sessions Request Info 2018/04/09-04/10
Serial Transceivers in 7 Series FPGAs/SoCs
Part III – Debugging Techniques and PCB Design
VILT 2 sessions Request Info 2018/01/15-01/16
VILT 2 sessions Request Info 2018/04/16-04/17
Serial Transceivers in UltraScale Series FPGAs/MPSoCs
Part I – Transceiver Design Methodology
VILT 2 sessions Request Info 2018/03/14-03/15
Serial Transceivers in UltraScale Series FPGAs/MPSoCs
Part II – Debugging Techniques and PCB Design
VILT 2 sessions Request Info 2018/03/21-03/22

Custom

Class Title Location Duration Price Click to Register for
Modular CoursesVILT Request Info Request Info